Technical Field
The present invention relates to a semiconductor device.
Background Art
In response to demand for a reduction in size and an increase in performance in power supply instruments in the field of power electronics in recent years, efforts have been focused on improving performance with respect to increasing breakdown voltage, increasing current, reducing loss, increasing breakdown resistance, and increasing speed in power semiconductors. A MOS power device driven by a MOS gate (an insulated gate formed of metal-oxide-semiconductor) is commonly known as a power semiconductor device wherein increasing current and reducing loss are possible.
Two kinds of structure are widely known as MOS gate structures of the MOS power device, those being a planar gate structure, wherein a MOS gate is provided in plate form on a semiconductor substrate, and a trench gate structure, wherein a MOS gate is embedded in a trench formed in a semiconductor substrate. The trench gate structure is attracting attention in recent vertical power devices, as the structure thereof is such that low on-state resistance characteristics are easily obtained.
A device wherein the surfaces of a p-type channel region and an n-type semiconductor substrate are disposed so as to appear alternately in a longitudinal direction between parallel trenches, and the surface form of an n+-type emitter region selectively formed in a surface layer of the p-type channel region is wider on the trench side and becomes narrower toward the center between trenches, has been proposed as a vertical MOS power device with this trench gate structure (for example, refer to PTL 1).
Also, as another vertical MOS power device, there have also been advancements in the development of a reverse conducting IGBT (RC-IGBT) of a structure wherein an insulated gate bipolar transistor (IGBT) and a freewheeling diode (FWD) connected in anti-parallel to the IGBT are integrated by being incorporated in the same semiconductor substrate (semiconductor chip), in order to achieve a reduction in size of a whole power conversion device.
A description will be given of an existing RC-IGBT. FIG. 18 is a plan view showing the structure of the existing RC-IGBT. FIG. 19 is a sectional view showing the sectional structure along a cutting line AA-AA′ of FIG. 18. As shown in FIGS. 18 and 19, the existing RC-IGBT includes a general field stop IGBT (FS-IGBT) and an FWD connected in anti-parallel to the FS-IGBT on the same n−-type semiconductor substrate, which forms an n−-type drift region 101.
Normally, in order to connect an FWD in anti-parallel to an FS-IGBT, an RC-IGBT has a structure wherein, taking a p-type base region configuring a MOS gate structure on the front surface side of an n−-type semiconductor substrate to be a p-type anode region 105-2, one portion of a p+-type collector region 111 provided on the back surface side of the n−-type semiconductor substrate is replaced with an n+-type cathode region 112. Specifically, an IGBT portion 121 in which an FS-IGBT is provided and an FWD portion 122 in which an FWD is provided are provided on the same n−-type semiconductor substrate.
A trench gate type MOS gate structure formed of a trench 102, gate insulating film 103, gate electrode 104, p-type base region 105-1, n+-type emitter region 106, and p+-type contact region 107, and an emitter electrode 109, are provided on the front surface side of the n−-type semiconductor substrate in the IGBT portion 121. The p-type base region 105-1 is disposed at predetermined intervals in the longitudinal direction of the trench 102 in a mesa portion (a region sandwiched between neighboring trenches 102) between neighboring trenches 102.
The trench gate formed of the trench 102, gate insulating film 103, and gate electrode 104 is provided in a stripe form extending in a direction (the longitudinal direction) perpendicular to the direction in which the IGBT portion 121 and FWB portion 122 are aligned (the lateral direction) from the IGBT portion 121 across the FWB portion 122. The p-type anode region 105-2 is provided over the whole of the front surface of the n−-type semiconductor substrate in a mesa portion between neighboring trenches 102 in the FWD portion 122.
The p-type anode region 105-2 is conductively connected to the emitter electrode 109. On the back surface side of the n−-type semiconductor substrate, the p+-type collector region 111 is provided in the IGBT portion 121 and the n+-type cathode region 112 is provided in the FWD portion 122. An n-type buffer layer 110 is provided between the p+-type collector region 111 and n+-type cathode region 112 and the n-type drift region 101. A collector electrode 113 is in contact with the p+-type collector region 111 and n+-type cathode region 112. Reference sign 108 is an interlayer dielectric.
A collector short device wherein a MOS gate structure is repeatedly disposed in a pattern the same as that of a normal IGBT on the front surface of a semiconductor chip, and an FWD portion n+-type cathode region and IGBT portion p+-type collector region are disposed in parallel on the back surface of the semiconductor chip, has been proposed as this kind of RC-IGBT (for example, refer to PTL 2).
Also, a device wherein an IGBT portion acting as an IGBT element and a diode region acting as a diode element are repeatedly, alternately disposed on a semiconductor substrate including an n−-type drift layer, and a p-type Schottky contact region that extracts holes from the n−-type drift layer is provided in a surface layer portion of the n−-type drift layer in a portion of the diode region farthest to the IGBT portion side, has been proposed as another RC-IGBT (for example, refer to PTL 3).
Also, a device of a structure wherein an emitter layer is provided in a first region on a first main surface side of a semiconductor substrate but no emitter layer is provided in a second region, and of a structure wherein a collector layer is provided in a first region on a second main surface side of the semiconductor substrate and a cathode layer is provided in a second region, has been proposed as another RC-IGBT (for example, refer to PTL 4).
Also, a device wherein multiple trench gates are formed at differing intervals on a substrate front surface side of a diode portion, and furthermore, an n-type emitter region and p-type base region are formed between trench gates formed at a shorter interval, has been proposed as another RC-IGBT (for example, refer to PTL 5).
Also, a semiconductor device that is a vertical diode including trenches on a substrate front surface side, wherein the trenches are disposed at differing intervals, and includes two regions, those being a region in which the intervals between trenches in the lateral direction of the trench are long and a region in which the intervals are short, has been proposed as a device including a mesa portion (for example, refer to PTL 6).
Also, the following device has been proposed as another RC-IGBT. Barrier metal is formed using titanium (Ti), tungsten (W), or the like on the surface of an interlayer dielectric and the inner surface of a second trench. An emitter (anode) electrode is in contact with a p-type base (anode) layer, an n-type emitter region, and a p-type contact region via the barrier metal (for example, refer to PTL 7 (Paragraphs 0054 and 0080, FIG. 5)).
Also, the following device has been proposed as another RC-IGBT. A back surface electrode is formed on a second main surface so as to be in contact with both a p-type collector region and an n-type cathode region, and has a titanium layer, a nickel (Ni) layer, and a gold (Au) layer stacked sequentially from the second main surface side. The titanium layer forms ohmic contact to both the p-type collector region and n-type cathode region (for example, refer to PTL 8).
Also, a device wherein IGBT regions and FWD regions are alternately provided adjacent to each other, and which has two kinds of FWD region of differing widths, has been proposed as another RC-IGBT (for example, refer to PTL 9 (Paragraph 0068, FIG. 6)). In PTL 9, by the width of an FWD region acting as a wide region (the distance between two channels sandwiching an FWD region acting as a narrow region) being 170 μm or more, the ratio of a region that does not function as an FWD region is relatively low, and forward voltage snapback is thus restricted.
Also, the following device has been proposed as another RC-IGBT. A floating layer deeper than an emitter region and contact region in a trench depth direction is provided in a p-type base layer of an IGBT portion. No floating layer or emitter region is provided in a diode portion. A gate electrode of the diode portion is of the emitter potential (for example, refer to PTL 10). In PTL 10, excessive hole implantation from the contact region of the IGBT portion to the diode portion is prevented by providing the floating layer.